a. Field of the Invention
The instant invention relates to DC-DC converters with synchronous rectifiers or other complementary switching devices. In particular, the instant invention relates to a method, system, and apparatus for determining dead times in DC-DC converters with synchronous rectifiers or other complementary switching devices.
b. Background Art
Because of significantly lower conduction losses compared to diode rectifiers, synchronous rectifiers are now used in essentially all low-voltage DC voltage regulators (e.g., DC power supplies), such as power supplies for battery-operated electronics, point-of-load converters, and microprocessor power supplies.
FIGS. 1 and 2, for example, show a synchronous buck DC-DC voltage regulator 100, together with typical control signal waveforms. The voltage regulator 100 includes a switched-mode power converter 102 (in this case, a buck power converter) and a controller 104. The buck power converter 102 shown in FIG. 1, for example, receives an input voltage Vg from a voltage source 106 and provides a regulated output voltage Vout to a load 108. The switched-mode power converter 102 includes a pair of complementary power switches. The pair of complementary power switches includes a main power switch 110 and a synchronous rectifier power switch 112. The power switches 110 and 112 are repeatedly turned on and off at a high switching frequency fs via the controller 104.
The controller 104 shown in FIG. 1 is a standard voltage-mode pulse-width modulated controller that senses an output voltage Vout of the converter 102 and compares that output voltage to a voltage reference Vref at a comparator 114 to obtain an error signal e. The comparator 114 provides the error signal e to a compensator 118 (also called an “error amplifier”) that amplifies the error signal to produce a duty-cycle command signal dc. The duty-cycle command signal dc is input to a pulse-width modulator (PWM) 120 that generates a periodic pulse-width modulated waveform g having a constant switching frequency fs and a duty-cycle determined by the duty-cycle command signal dc. From the periodic pulse-width modulated waveform g, a dead-time circuit 126 generates two gate-drive control signals g1 and g2 to control the on/off states of the complementary power switches 110 and 112 through appropriate gate-drive circuits 122 and 124, respectively, as shown in FIG. 1.
“Dead-times” td1 and td2 are the relatively short time intervals and when both gate-drive signals vg1 and vg2 are inactive, i.e., when both complementary power switches 110 and 112 are off, as illustrated by the typical waveforms shown in FIG. 2.
Optimum utilization of a synchronous rectifier depends on the ability of the dead-time circuit 126 to optimally adjust the commutating dead-times td1 and td2. Too long dead times (as in the waveforms shown in FIG. 2) result in additional losses due to conduction and reverse recovery of the body diodes of the power switches 110 and 112. Too short (or negative) dead-times may result in simultaneous conduction of the main power switch 110 and the synchronous rectifier power switch 112, resulting in large current spikes through the devices and even more adverse penalties in the converter efficiency.
Various schemes have been proposed to address the desired synchronous rectifier commutation problem, i.e., the determination of dead-times that result in the highest possible power conversion efficiency η=Pout/Pin. In the simplest circuit realizations, the dead-times have constant values. In the presence of parameter tolerances, temperature variations or operating point changes, this simplest approach of fixed dead times often yields severely degraded efficiency, especially in converters operating at relatively high switching frequencies (in the hundreds of kHz to megahertz range).
Previously proposed schemes for improved synchronous rectifier commutation have been based on the idea that the synchronous rectifier should commutate as an ideal rectifier; it should be turned on exactly at the time when the voltage across it drops to zero, and it should be turned off exactly at the time when the current through it drops to zero. See, e.g., P. T. Krein and R. M. Bass, “Autonomous control technique for high-performance switches,” IEEE Transactions on Industrial Electronics, Vol. 39, No. 3, June 1992, pp. 215-22. Direct implementation of this idea requires sensing the zero-crossing of the voltage v, across the synchronous rectifier, and sensing the threshold-crossing of the gate-drive voltage, which is indicative of the turn-on (or the turn-off) instant. In “adaptive” gate-drive schemes, fast comparators attempt to match the zero-crossing of the voltage vs and the threshold-crossing instants in each switching cycle, which in practice results in sub-optimal performance because of the comparator delays and sensitivity to parameter and temperature variations.
Better results have been reported with schemes based on the “predictive” gate drive technique such as described in S. Mapus, “Predictive gate drive boosts synchronous dc/dc power converter efficiency,” Texas Instruments Application Report, SLUA281, April 2003 (the “Mapus reference”), or with various delay-locked loop circuits such as described in B. Acker et al., “Synchronous rectification with adaptive timing control,” IEEE PESC 1995, pp. 88-95; and W. Lav and S. R. Sanders, “An integrated controller for a high frequency buck converter,” IEEE PESC 1997, pp. 246-54. These techniques can reduce the dependence on very fast comparators and the sensitivity to parameter or temperature variations. They are still based on sensing the noisy switch voltage vs, and on the ability to accurately detect and control turn-on and turn-off instants, which can be difficult, especially if the gate drivers and the power MOSFETs are not integrated on the same die. Furthermore, such schemes are implemented using analog circuitry, and are available only through specialized, more complex gate drivers such as disclosed in the Mapus reference.
Another scheme for improved synchronous rectifier commutation attempts to increase efficiency directly by minimizing the measured power loss or measured input current. Some such attempts to directly maximize the power conversion efficiency η(td1, td2) on-line via minimizing the measured power loss or measured input current, for example, are described in J. Kimbal, P. T. Krein, “Continuous-time optimization of gate timing for synchronous rectification,” IEEE Midwest Symp, 1997, pp. 1015-18; A. V. Peterchev, S. R. Sanders, “Digital loss-minimizing multimode synchronous buck converter control,” IEEE PESC 2004, pp. 3694-99; and J. A. Abu-Qahouq, H. Mao, H. J. Al-Atrash, I. Batarseh, “Maximum efficiency point tracking (MEPT) method and dead time control,” IEEE PESC 2004, pp. 3700-06. Although possible in principle, these approaches require sensing or computing the input power or losses, which are difficult to accomplish in practice. In the Abu-Qahouq et al. reference, for example, the input current of the converter is sensed and averaged, and an algorithm is used to search for dead-times that minimize the average input current. Actually measuring the input current, however, is often difficult to implement due to noisy input current sensing conditions, lengthy time durations required to average the input currents, complicated high-resolution current sensing circuitry, and sensitivity due to input-current variations caused by disturbances other than dead-times.